University of Minnesota, PhD Candidate
Key-Based Dynamic Functional Obfuscation of Integrated Circuits using Sequentially-Triggered Mode-Based Design
This work proposes a novel technique for hardware obfuscation termed dynamic functional obfuscation. Hardware obfuscation refers to a set of countermeasures used against IC counterfeiting and illegal overproduction. Traditionally, obfuscation encrypts semiconductor circuits using key inputs which must be set to a correct value to operate the circuit correctly.
By keeping the key values secret during the manufacturing process, any attempt by unauthorized parties to overproduce chips or pirate designs is thwarted. The proposed dynamic technique differs from existing fixed obfuscation schemes as the obfuscating signals change over time. This results in inconsistent circuit behavior upon input of incorrect key, where the chip operates correctly sometimes and fails sometimes. The advantage of dynamic obfuscation is that it results in stronger obfuscation by increasing the time complexity of deciphering the correct key using brute-force attack, even with shorter keys. Moreover, the dynamic nature of these circuits also makes them resistant to reverse engineering and SAT solver based attacks. To achieve dynamic obfuscation, ideas from hardware trojan literature and sequentially triggered counters are utilized. A demonstration of obfuscation on sequential circuits implementing fast Fourier transform (FFT) algorithm and Ethernet IP shows low overall area and power overheads of less than 1%. Security in terms of time to attack for the FFT circuit (for a key size of 30 bits and a system operating at 100 MHz) is increased to 1,021,055 years using dynamic obfuscation compared to only 5.36 s using fixed obfuscation schemes. For the Ethernet IP core, time to attack of dynamic obfuscation with a key size of 32 bits is 1,046,423,135 years compared to 21.47s with fixed obfuscation. It is also shown that for a key size of K bits, the lower bound for time to attack using brute-force is proportional to exponential of the key size for the proposed design using one and two random number generators, respectively.
I am an international student at the University of Minnesota pursuing a PhD in Electrical Engineering, currently in my final year. I am working under the guidance of Professor Keshab Parhi on architectures for hardware security, cryptography and low-power solutions targeted at various applications. Specifically, I am working on development of novel methods of obfuscation, study and implementation of authenticated encryption schemes and application of approximate computing techniques for biomedical applications such as Seizure Detection.
I completed a Masters degree in Electrical Engineering from the University of Minnesota in 2014 and a Bachelors degree in Electronics and Communication Engineering from Visvesvaraya Technological institute, India in 2010. Apart from working in the lab of Professor Keshab Parhi, I have also worked on a collaborated project in Hardware Security with Professor Chris Kim. The project titled “Design of Secure and Anti-Counterfeit Integrated Circuits” is funded by Semiconductor Research Corporation (SRC) and National Science Foundation (NSF). I have worked as a Project Assistant in the lab of Professor S.K. Nandy at the Computer Aided Design Lab at Indian Institute of Science (IISc), Bangalore, India. As part of industrial research experience, I have interned for 6 months at the Security Center for Excellence, Intel Corporation as a Security Research intern.
I have a strong background in Modern Cryptography, VLSI Design, Computer Architecture, Signal Processing and Machine Learning. I have published papers in 2 journals and 5 conferences so far. I have been awarded the Best-in-Session award at SRC TECHCON 2016, ISCAS 2017 Student Travel Grant and the CAS Society Travel Grant award for 2017. I have also been selected to present my dissertation work at the DAC PhD Forum.
I wish to pursue a career as a hardware architect specializing in applications of hardware security and machine learning. With the upcoming Internet-of-Things (IoT) era, I believe there will be exciting new challenges which need to be jointly addressed by both academia and industry.